1 clock module top_module ( ); reg clk; dut U1(.clk(clk)); initial begin clk = 0; end always begin #5; clk = ~clk; end endmodule 2 Tb/tb1 module top_module ( output reg A, output reg B
专注分享技术,共同学习,共同进步。侵权联系[81616952@qq.com]
Copyright (C)ICode9.com, All Rights Reserved.
ICode9版权所有