标签:10 begin end Testbenches clk module Writing Verification reg
1 clock
module top_module ( );
reg clk;
dut U1(.clk(clk));
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
endmodule
2 Tb/tb1
module top_module ( output reg A, output reg B );//
// generate input patterns here
initial begin
A = 0;
B = 0;
#10;
A = 1;
#5;
B = 1;
#5;
A = 0;
#20;
B = 0;
end
endmodule
3 Tb/and
module top_module();
reg a,b,out;
initial begin
a = 0;
b = 0;
#10;
a = 0;
b = 1;
#10;
a = 1;
b = 0;
#10;
a = 1;
b = 1;
end
andgate U1({a,b},out);
endmodule
4 Tb/tb2
module top_module();
reg clk;
reg in;
reg [2:0] s;
reg out;
q7 U1(.clk(clk), .in(in), .s(s), .out(out));
initial begin
clk = 0;
in = 0;
s = 3'd2;
#10;
in = 0;
s = 3'd6;
#10;
in = 1;
s = 3'd2;
#10;
in = 0;
s = 3'd7;
#10;
in = 1;
s = 3'd0;
#30;
in = 0;
end
always begin
#5;
clk = ~clk;
end
endmodule
5 Tb/tff
module top_module ();
reg clk,reset,t,q;
tff U1(.clk(clk),
.reset(reset),
.t(t),
.q(q));
initial begin
clk = 0;
t = 0;
reset = 0;
end
always begin
#5;
clk = ~clk;
end
initial begin
reset = 1'b0;
#3;
reset = 1'b1;
#10;
reset = 1'b0;
end
always@(posedge clk)begin
if(reset)
t = 1;
else
t = 0;
end
endmodule
标签:10,begin,end,Testbenches,clk,module,Writing,Verification,reg 来源: https://www.cnblogs.com/hubuguilai/p/16650793.html
本站声明: 1. iCode9 技术分享网(下文简称本站)提供的所有内容,仅供技术学习、探讨和分享; 2. 关于本站的所有留言、评论、转载及引用,纯属内容发起人的个人观点,与本站观点和立场无关; 3. 关于本站的所有言论和文字,纯属内容发起人的个人观点,与本站观点和立场无关; 4. 本站文章均是网友提供,不完全保证技术分享内容的完整性、准确性、时效性、风险性和版权归属;如您发现该文章侵犯了您的权益,可联系我们第一时间进行删除; 5. 本站为非盈利性的个人网站,所有内容不会用来进行牟利,也不会利用任何形式的广告来间接获益,纯粹是为了广大技术爱好者提供技术内容和技术思想的分享性交流网站。