DSP28335中spi的配置------mcbsp配置&自带的spi配置

2021-02-26 16:06:00 阅读：384 来源： 互联网

标签：GpioCtrlRegs PCR 配置 spi Enable GPIO57 McbspbRegs bit DSP28335

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之前写过一个dsp驱动w5200以太网的驱动，分别用到如题的两种方式，网上很多例子不够完善，这里给出详细代码。

下面简单介绍下配置要点和收发等情况；
spi的引脚控制主要用到
SPISOMI: 主入从出
SPISIMO:主出从入
SPICLK：时钟

第一种方式：mcbsp配置成spi
—————————————————–mcbsp—————————————————————————————-

void LAN1_Gpio(void)
{
//mcbspb 做spi，
EALLOW;

GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (SPISIMO)
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (SPISOMI)
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (SPICLK)

GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 3; // Asynch input GPIO24 (SPISIMO)
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (SPISOMI)
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26 (SPICLK)
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (SPISTE)
//下面的值是3
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // Configure GPIO24 as SPISIMO
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // Configure GPIO25 as SPISOMI
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // Configure GPIO26 as SPICLK

//Configure GPIO49 as RESET
GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0;// Enable pullup
GpioDataRegs.GPBSET.bit.GPIO49 = 1; // Load output latch
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 0; //
GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1; // GPIO49 = output

//Configure GPIO27 as SPISTEA
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0;// Enable pullup
GpioDataRegs.GPASET.bit.GPIO27 = 1; // Load output latch
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; //
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1; // GPIO27 = output

EDIS;

}

#define RD =1;//编译控制字根据自己的芯片进行选择

void LAN1_Init()
{
// McBSP register settings
McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspbRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
McbspbRegs.SPCR1.bit.DLB = 0;
McbspbRegs.PCR.bit.CLKXM = 1;
McbspbRegs.PCR.bit.CLKRM = 1;

McbspbRegs.PCR.bit.SCLKME = 0;//SCLKME = 0,CLKSM =1,选择LSPCLK时钟源
McbspbRegs.SRGR2.bit.CLKSM = 1;
McbspbRegs.SRGR2.bit.FPER = 1;//

McbspbRegs.PCR.bit.FSRM = 1;//接收帧同步模式

McbspbRegs.SRGR1.bit.CLKGDV = 1; // Frame Width = 1 ,CLKG period,一分频2017.12.29
McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period

#if RND
McbspbRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspbRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0
McbspbRegs.PCR.bit.CLKRP = 0;
#endif
#if RD
McbspbRegs.SPCR1.bit.CLKSTP = 3; // Together with CLKXP/CLKRP determines clocking scheme
McbspbRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 1
McbspbRegs.PCR.bit.CLKRP = 1;
#endif
#if FND
McbspbRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspbRegs.PCR.bit.CLKXP = 1; // CPOL = 1, CPHA = 0
McbspbRegs.PCR.bit.CLKRP = 0;
#endif
#if FD
McbspbRegs.SPCR1.bit.CLKSTP = 3; // Together with CLKXP/CLKRP determines clocking scheme
McbspbRegs.PCR.bit.CLKXP = 1; // CPOL = 1, CPHA = 1
McbspbRegs.PCR.bit.CLKRP = 1;
#endif

McbspbRegs.RCR2.all=0x0001; // Single-phase frame, 1 word/frame, No companding (Receive)
McbspbRegs.RCR1.all=0x0000; // Default 8-bits per word. Note, phase 2 bits should be ignored.

McbspbRegs.XCR2.all=0x0001; // Single-phase frame, 1 word/frame, No companding (Transmit)
McbspbRegs.XCR1.all=0x0000; // Default 8-bits per word. Note, phase 2 bits should be ignored.

McbspbRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 2^6 CLKG periods
McbspbRegs.SRGR1.all=0x000F; // Frame Width = 1 CLKG period, CLKGDV=2
McbspbRegs.SPCR1.bit.DXENA=1;
McbspbRegs.SPCR2.bit.XINTM = 0;
McbspbRegs.SPCR1.bit.RINTM = 0;
McbspbRegs.MFFINT.bit.RINT = 0;
McbspbRegs.XCR2.bit.XDATDLY = 1;//1位延迟位,stop mode 必须置1
McbspbRegs.RCR2.bit.RDATDLY = 1;//1位延迟位，stop mode 必须置1
McbspbRegs.RCR1.bit.RWDLEN1=0; // 16-bit word
McbspbRegs.XCR1.bit.XWDLEN1=0; // 16-bit word
delay_loop();
McbspbRegs.SPCR2.all |=0x00C1; // Frame sync & sample rate generators pulled out of reset
McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
McbspbRegs.SPCR2.bit.XRST=1; // Enable Transmitter
McbspbRegs.SPCR1.bit.RRST=1; // Enable Receiver

}

注意：spi虽然配置为8bit收发，但是dsp是16位收发，而且dsp在发数据时候是高位数据有效，收数据是低位数据有效。

第二种方式：自带的spi配置
—————————————————–dsp自带的spi配置————————————————————

/******************************************************************************
* FUNCTION初始化外围接口
* LAN2初始化对应SPIB总线
* 1、MISO\MOSI\CLK引脚初始化
* 2、设置CS片选，高电平输出
******************************************************************************/
void LAN2_Gpio(void)
{
EALLOW;
GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA)
GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA)
GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA)

GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO54 (SPISIMOA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO55 (SPISOMIA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO56 (SPICLKA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO57 (SPISTEA)

GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA

//Configure GPIO53 as RESET
GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0;// Enable pullup
GpioDataRegs.GPBSET.bit.GPIO53 = 1; // Load output latch
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 0; // GPIO57 = GPIO57
GpioCtrlRegs.GPBDIR.bit.GPIO53 = 1; // GPIO57 = output

//Configure GPIO57 as SPISTEA
GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0;// Enable pullup
GpioDataRegs.GPBSET.bit.GPIO57 = 1; // Load output latch
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0; // GPIO57 = GPIO57
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1; // GPIO57 = output

EDIS;

}

void LAN2_Init()
{
SpiaRegs.SPICCR.all =0x0007; //Reset off, rising edge, 8-bit char bits
SpiaRegs.SPICTL.all =0x000e; //Enable master mode, delayed phase,
//enable talk, and SPI int disabled.
SpiaRegs.SPIBRR =0x0063; //LSP37.5M 波特率=37.5/（BRR+1）波特率设置为375000
SpiaRegs.SPISTS.all=0x0000; //清标志
SpiaRegs.SPICCR.all =0x0087; //Relinquish SPI from Reset
SpiaRegs.SPIPRI.bit.FREE = 0x0001; //Transmission not affected by emulator
SpiaRegs.SPICCR.bit.SPISWRESET=1; // SPI软复位//-------------2018/7/17缺少就会接收卡死
}

两种模式的收发也是不一样的，稍注意下。
各种细节都在代码里了，根据要驱动的芯片进行改动即可，如果是w5500、w5200等以太网芯片，直接可用。
关于驱动dsp驱动12864等，主要是控制上电时序，引脚电平，配置spi。细节不再多讲。

标签：GpioCtrlRegs,PCR,配置,spi,Enable,GPIO57,McbspbRegs,bit,DSP28335
来源： https://blog.csdn.net/kunkliu/article/details/114136552

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DSP28335中spi的配置------mcbsp配置&自带的spi配置