标签:ctrl Princeton implementation RTL instruction datapath ELE each cycle
Big Picture: Classic 5 Components of A Processor
-- Control Unit (in the processor)
-- Datapath (in the processor)
-- Memory
-- Input
-- Output
HARDWARE DESIGN STEPS
1. analyze instruction set => datapath requirements
ISA model => RTL model: the meaning of each instruction is given by the register transfers
datapath must include storage element of ISA registers and possibly more
datapath must support each register transfer
2. select set of datapath componets and build clocking methodology
3. assemble datapath meeting the RTL requirements
4. analyze implementation of each instruction to determine setting of ctrl points that effect the register transfer
5. assemble the ctrl logic
6. RTL datapath and ctrl design are refined
timing and bug-fixing
optimization for cost/performance (computering engineering is all about trade-off)
SELECT A SUBSET OF INSTRUCTIONS
LOOK AT WHAT HAPPENS ON EACH INSTRUCTION
- 取出指令
- 解码并执行
MORE DETAILED DECOMPOSITION
- 取指 PC specifies a instruction and it get fetched from memory
- 解码 figure out every field of the instruction; read 1 or 2 regs as operands
- 执行 ALU does the math
- 访存 read a data for a LOAD; write a data for a STORE
- 回写 store results to memory or registers
5 steps done in a clock cycle
purely combinational logic in that rectangle
this is what single-cycle computer means
标签:ctrl,Princeton,implementation,RTL,instruction,datapath,ELE,each,cycle 来源: https://www.cnblogs.com/ELE-more-fun/p/12976593.html
本站声明: 1. iCode9 技术分享网(下文简称本站)提供的所有内容,仅供技术学习、探讨和分享; 2. 关于本站的所有留言、评论、转载及引用,纯属内容发起人的个人观点,与本站观点和立场无关; 3. 关于本站的所有言论和文字,纯属内容发起人的个人观点,与本站观点和立场无关; 4. 本站文章均是网友提供,不完全保证技术分享内容的完整性、准确性、时效性、风险性和版权归属;如您发现该文章侵犯了您的权益,可联系我们第一时间进行删除; 5. 本站为非盈利性的个人网站,所有内容不会用来进行牟利,也不会利用任何形式的广告来间接获益,纯粹是为了广大技术爱好者提供技术内容和技术思想的分享性交流网站。