HDLBits_for_?_generate

2021-11-29 23:30:52 阅读：249 来源： 互联网

标签：HDLBits always module vector output input generate out

More Verilog Features

Conditional

Verilog has a ternary conditional operator ( ? : ) much like C:

(condition ? if_true : if_false)

This can be used to choose one of two values based on condition (a mux!) on one line, without using an if-then inside a combinational always block.

Examples:
(0 ? 3 : 5)     // This is 5 because the condition is false.
(sel ? b : a)   // A 2-to-1 multiplexer between a and b selected by sel.

always @(posedge clk)         // A T-flip-flop.
  q <= toggle ? ~q : q;

always @(*)                   // State transition logic for a one-input FSM
  case (state)
    A: next = w ? B : A;
    B: next = w ? A : B;
  endcase

assign out = ena ? q : 1'bz;  // A tri-state buffer

((sel[1:0] == 2'h0) ? a :     // A 3-to-1 mux
 (sel[1:0] == 2'h1) ? b : c )

Reduction

You’re already familiar with bitwise operations between two values, e.g., a & b or a ^ b. Sometimes, you want to create a wide gate that operates on all of the bits of one vector, like (a[0] & a[1] & a[2] & a[3] … ), which gets tedious if the vector is long.

The reduction operators can do AND, OR, and XOR of the bits of a vector, producing one bit of output:

& a[3:0]     // AND: a[3]&a[2]&a[1]&a[0]. Equivalent to (a[3:0] == 4'hf)
| b[3:0]     // OR:  b[3]|b[2]|b[1]|b[0]. Equivalent to (b[3:0] != 4'h0)
^ c[2:0]     // XOR: c[2]^c[1]^c[0]
These are unary operators that have only one operand (similar to the NOT operators ! and ~). You can also invert the outputs of these to create NAND, NOR, and XNOR gates, e.g., (~& d[7:0]).

XOR ^ 异或

Vector100r

for(int i=0;i<100;i=i+1)

Popcount255

题目：A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 255-bit input vector.

module top_module( 
    input [254:0] in,
    output [7:0] out );
    
    always @(*) begin
        for (int i=0;i<255;i++)begin
            if (in[i]==1)
                out=out+1;
        end
    end

endmodule

错误原因：未定义初始值

module top_module (
	input [254:0] in,
	output reg [7:0] out
);

	always @(*) begin	// Combinational always block
		out = 0;
		for (int i=0;i<255;i++)
			out = out + in[i];
	end
	
endmodule

Adder100i

注意符号不要打错，错误原因为将+打成=

Bcdadd100

题目：You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

module bcd_fadd {input [3:0] a,input [3:0] b, input cin,output cout,output [3:0] sum );
Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    reg [99:0]w1;
    genvar i;
    bcd_fadd bcd1(a[3:0],b[3:0],cin,w1[0],sum[3:0]);
	generate 
        //near text: "int";  expecting an identifier ("int" is a reserved keyword )
        for (i=1;i<99;i++)
            begin:zpz//this block requires a name File
                bcd_fadd bcd(a[(4*(i+1)-1):(4*i)],b[(4*(i+1)-1):(4*i)],w1[i-1],w1[i],sum[(4*(i+1)-1):(4*i)]);
                //forget cout:w[i]
                //wrong:sum[(4*(i+1)-1):(4*i-1)]For:[(4*i-1)]repeat
        end
    endgenerate
    bcd_fadd bcd2(a[399:396],b[399:396],w1[98],cout,sum[399:396]);
endmodule

标签：HDLBits,always,module,vector,output,input,generate,out
来源： https://blog.csdn.net/m0_57142809/article/details/121611874

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