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verilog练习题Exams/2012 q2b

2021-11-03 20:01:18  阅读:133  来源: 互联网

标签:练习题 q2b STATE hot state input parameter assign 2012


Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)

Write a logic expression for the signal Y1, which is the input of state flip-flop y[1].

Write a logic expression for the signal Y3, which is the input of state flip-flop y[3].

(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

答案:

module top_module (
    input [5:0] y,
    input w,
    output Y1,
    output Y3
);

parameter A_STATE = 7'b000001;
parameter B_STATE = 6'b000010;
parameter C_STATE = 6'b000100;
parameter D_STATE = 6'b001000;
parameter E_STATE = 6'b010000;
parameter F_STATE = 6'b100000;

wire [5:0] n_state;

//assign n_state = y;
always @(*) begin
case (y)
    A_STATE: n_state = (w) ? B_STATE:A_STATE;
    B_STATE: n_state = (w) ? C_STATE:D_STATE;
    C_STATE: n_state = (w) ? E_STATE:D_STATE;
    D_STATE: n_state = (w) ? F_STATE:A_STATE;
    E_STATE: n_state = (w) ? E_STATE:D_STATE;
    F_STATE: n_state = (w) ? C_STATE:D_STATE; 
    default:; 
endcase    
end

assign Y1 = (n_state == B_STATE) ?1:0;
assign Y3 = (n_state == E_STATE) ?1:0;


endmodule

看了网上别的答案可以直接用组合逻辑判断。代码行数也少,比较好

 

标签:练习题,q2b,STATE,hot,state,input,parameter,assign,2012
来源: https://blog.csdn.net/u012780083/article/details/121129130

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